1. Field of the Invention
The present invention generally relates to a semiconductor device and fabrication method thereof and, more particularly, to a non-volatile memory device having a MONOS (Metal-Oxide-Nitride-Oxide-Semiconductor) gate structure and a fabrication method thereof.
2. Description of the Related Art
Semiconductor memory devices for storing data can typically be categorized as either volatile memory devices or non-volatile memory devices. Volatile memory devices lose their stored data when their power supplies are interrupted, whereas non-volatile memory devices retain their stored data when their power supplies are interrupted. Thus, non-volatile memory devices, e.g., flash memory devices are widely used in a mobile telecommunication system or a memory card.
Generally, a stacked gate structure is employed in a cell transistor of the non-volatile memory device. The stacked gate structure includes a tunnel oxide layer, a floating gate, an inter-gate dielectric layer and a control gate, which are sequentially stacked on a channel region of the cell transistor. This stacked gate structure causes a severe step difference between a cell array region and a peripheral circuit region. Consequently, subsequent processing steps can be complicated and difficult to execute. In addition, the process for forming the floating gate is complex and it is difficult to increase a surface area of the floating gate. The surface area of the floating gate influences a coupling ratio of the cell transistor, and the coupling ratio affects the program characteristic and erase characteristic of the cell transistor. Therefore, it is required to increase the surface area of the floating gate in order to improve the program characteristic and the erase characteristic. However, in a highly integrated non-volatile memory device, there is a limit to increasing the surface area of the floating gate.
A cell transistor having a MONOS gate structure has been proposed in order to solve the above problems of the non-volatile memory device having the stacked gate structure.
A fabrication method of non-volatile memory device having the MONOS gate structure is taught in U.S. Pat. No. 6,103,572 entitled xe2x80x9cMethod of fabricating a semiconductor non-volatile storage devicexe2x80x9d by Kirihara, which is incorporated herein by reference. According to Kirihara, an interconnection electrode and a passivation layer are formed on a semiconductor substrate including a cell transistor having a MONOS gate structure, and the passivation layer is annealed at a temperature of 425xc2x0 C. and in a nitrogen atmosphere. In addition, the interconnection electrode is annealed at a temperature of 380xc2x0 C. and in a hydrogen atmosphere, prior to formation of the passivation layer. Thus, the annealing processes remove electric charges trapped in the MONOS gate structure during a plasma etching process for forming the interconnection electrode and a plasma CVD process for depositing the passivation layer. As a result, the initial threshold voltage of the cell transistor can be stabilized.
On the other hand, a non-volatile memory device such as a NAND type flash memory device contains low-voltage MOS transistors and high-voltage MOS transistors within a peripheral circuit area thereof, and contains cell transistors and selection transistors within a cell array area thereof. The low-voltage MOS transistors are mostly operated in a read mode, and the high-voltage MOS transistors are mainly operated in a program mode and an erase mode. Also, high voltage and low voltage are applied to the cell transistors, and low voltage is applied to the selection transistors. Therefore, in non-volatile memory devices employing the cell transistor having the MONOS gate structure, it is required to optimize gate structures of the low-voltage MOS transistors, the high-voltage MOS transistors and the selection transistors.
The present invention provides non-volatile memory devices including selection transistors, low-voltage MOS transistors and high-voltage MOS transistors as well as cell transistors having the MONOS gate structure.
According to one embodiment of the present invention, the non-volatile memory device of the invention comprises a cell array area and a peripheral circuit area. The cell array area includes a selection transistor and a cell transistor, and the peripheral circuit area includes a low-voltage MOS transistor and a high-voltage MOS transistor. The cell transistor contains a cell gate pattern having a MONOS structure. In detail, the cell gate pattern contains a cell gate insulation layer having a tunnel oxide layer, a silicon nitride layer pattern and a top oxide layer pattern, which are sequentially stacked on a semiconductor substrate, and a cell gate electrodes disposed on the cell gate insulation layer. Also, the low-voltage MOS transistor includes a low-voltage gate insulation layer and a low-voltage gate electrode, and the high-voltage MOS transistor contains a high-voltage gate insulation layer and a high-voltage gate electrode. The high-voltage gate insulation layer is a first oxide layer, and the low-voltage gate insulation layer is a second gate oxide layer, thinner than the first gate oxide layer. The thickness of the second gate oxide layer is less than the equivalent oxide thickness of the cell gate insulation layer.
In accordance with one aspect of the present invention, the selection transistor comprises a selection gate pattern having a selection gate insulation layer and a selection gate electrode, which are sequentially stacked. The selection gate insulation layer is the same material layer as the second gate oxide layer.
According to another aspect of the present invention, the selection gate insulation layer may be the same material layer as the cell gate insulation layer.
According to another embodiment of the invention, the present invention also provides a fabrication method of a non-volatile memory device including a MONOS gate structure. This method comprises forming an isolation layer on a predetermined region of a semiconductor substrate having a cell array area and a peripheral circuit area. The isolation layer defines a first active region in the cell array area and a second and third active regions in the peripheral circuit area. A tunnel oxide layer, a silicon nitride layer and a top oxide layer are sequentially formed on the surface of the substrate having the isolation layer. The top oxide layer, the silicon nitride layer and the tunnel oxide layer are patterned to form a cell gate insulation layer covering the first active region and expose the active regions of the peripheral circuit area, i.e., the second and third active regions of the peripheral circuit area. The cell gate insulation layer includes the patterned tunnel oxide layer, the pattern silicon nitride layer and the patterned top oxide layer. At this time, a portion of the first active region, i.e., a first area can be exposed. Thus, the cell gate insulation layer may cover only a second area of the first active region.
A first gate oxide layer is formed on the exposed second and third active regions. At this time, if the first area of the first active region is exposed, the first gate oxide layer is also formed on the exposed first area. The first gate oxide layer is then patterned to expose the second active region. At this time, if the first gate oxide layer is formed on the exposed first area, the first area is also exposed.
A second gate oxide layer, which is thinner than the first gate oxide layer, is formed on the exposed second active region. If the first area is exposed by patterning the first gate oxide layer, the second gate oxide layer is also formed on the first area. The thickness of the second gate oxide layer is less than the equivalent oxide thickness of the cell gate insulation layer.
In addition, a conductive layer is formed on the entire surface of the substrate including the second gate oxide layer. The conductive layer is patterned to form a cell gate electrode crossing over the second area of the first active region, a selection gate electrode crossing over the first area of the first active region, a low-voltage gate electrode crossing over the second active region and a high-voltage gate electrode crossing over the third active region.